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Dept. of E&C Engineering celebrated AARADHANA 2K19

07-May-2019
Dept. of E&C Engineering celebrated AARADHANA 2K19

The Valedictory ceremony of AEnCES was held in the campus with the theme - “Aaradhana”, The Tradition. Mr. Vardhana M, an alumnus, design engineer at NXP semiconductors was the special invitee for the function. Vice-Principal Prof. S S Balakrishna presided the programme. Dr. Ashwath Rao, Head of Dept. of E&C Engineering; AEnCES coordinator Mr. Gurusiddayaa Hiremath; President Mr. Vishwanath Pai was also present. Mr. Vardhana M is an experienced Design Engineer working in the semiconductors industry. His areas include Verification and Validation (V&V), SV, Scripting, Universal Verification Methodology (UVM), and Visual Basic for Application. A technical talk on VLSI design methodologies- ASIC and FPGA to all the E&C Engineering students was held and was very effective. He emphasized on design flow of ASICS and FPGA and also their differences. He also spoke about the required skills an engineer should possess and closed the session by explaining the various case studies on implementation of image processing on FPGA. The function concluded with the cultural extravaganza.

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